IBM stacks up a sub-nanometer chip future (opens original article in a new tab)

IBM unveils sub-nanometer chip technology with 0.7 nm process node, featuring 3D nanostack architecture that improves performance and efficiency, with potential applications in AI and other computing fields.

• IBM develops sub-nanometer chip technology with 0.7 nm (7 Angstroms) process node, enabling higher transistor density
• Nanostack architecture uses 3D transistor stacking with staggered layers and independent contact for signal and power
• IBM claims 50% performance improvement or 70% efficiency gain over 2 nm technology, with roadmap to 1 Angstrom